A digital servo system is highly effective for a motor driven apparatus such as a video tape recorder (referred to as a VTR hereafter), which demands a high degree of precision and stabilization for various motor speeds.
FIG. 1 shows the construction of a conventional digital frequency discriminator of a digital servo system used, for example, in VTRs. In FIG. 1, a clock signal CK is applied to a sequencer 20 and an AND gate 21, through a clock input terminal 22. The sequencer 20 and the AND gate 21 constitute a system control section of this digital frequency discriminator, as described later. The sequencer 20 also is applied through a data input terminal 23 with a digital data FG which is to be processed in this digital frequency discriminator. The digital data FG is generated by a rotation speed detector (not shown) for a capstan motor of VTRs. The sequencer 20 is so designed as to generate various control signal, such as a stop signal STOP, a latch signal LATCH and a preset signal PRESET, as shown in FIG. 2, in response to every pulse of the digital data FG. Those signals STOP, LATCH and PRESET are generated at times, as shown in FIG. 2, in synchronization with the clock signal CK.
The construction and the operation of the conventional digital frequency discriminator will be explained in reference to FIGS. 1 and 2. The stop signal STOP generated by sequencer 20 is applied to the AND gate 21. Then, the stop signal STOP prohibits the clock signal CK to transmit therethrough when the stop signal STOP is a low level (referred as the L level hereafter). Otherwise the clock signal CK is applied to a presettable up-counter 24 (hereafter referred to as `up-counter`). The latch signal LATCH generated by sequencer 20 is applied to the latch input terminals of latch circuits 25 and 26 at a prescribed time after the operation of the up-counter 24 has been stabilized, for instance after five pulses of the clock signal CK have been applied. When the latch signal LATCH is applied, the latch circuit 25 latches L bits from the LSB (Least Significant Bit) of the count data of the up-counter 24. On the other hand, the latch circuit 26 latches a linear range indication signal F and a carry indication signal G, which will be described later. Those signals F and G are decoded by a decoder 27 from M bits from the MSB (Most Significant Bit) of the count data of the up-counter 24. After those latch operations have been completed in the latches 25 and 26, the preset signal PRESET generated by the sequencer 20 is applied to the preset terminal of the up-counter 24. As a result, a predetermined data NP stored in a ROM (Read Only Memory) 28 is preset in the up-counter 24.
After the preset of the data NP into the up-counter 24, the stop signal STOP turns to a high level (referred as the H level hereafter) so that the AND gate 21 allows the clock signal CK to transmit therethrough. The up-counter 24 begins its count operation and counts up from the value of the data NP preset as an initial value.
Decoder 27 judges the content of the M bits of the count data of the up-counter 24. When the M bits are all "1", the decoder 27 generates the linear range indication signal F. The signal F indicates that the operation of this digital frequency discriminator is in a linear detection characteristic range. Moreover, the decoder 27 detects an over-flow condition of the count operation in the up-counter 24 so that the carry indication signal G is generated. The operation of the decoder 27 will be explained below in more detail, in reference to FIG. 3.
As shown in FIG. 3, the up-counter 24 begins its count operation and counts up from the value of the data NP preset as the initial value, as described before, when a pulse FG1 of the digital data FG is applied. A saw-tooth waveform graph CNTa, shown by a solid line in the drawing, shows the variation of the count data in the up-counter 24. Now, it is assumed that the M bits applied to decoder 27 are three bits, the content of the L bits applied to the latch circuit 25 changes three times repeatedly until the M bits become all "1", as shown by another saw-tooth waveform graph CNTb with a broken line in the drawing.
Here, it is also assumed that a second pulse FG2 of the digital data FG appears at the position of the time axis, as shown by the dotted line in the drawing. Then, the L bits with approximately a value of the graph CNTb at a time t1, as shown in the drawing, is latched in the latch 25. Since the second pulse FG2 is in the linear range of the graph CNTb, an output data of the latch 25 is applied to an external circuit (not shown), e.g., a pulse width modulation circuit. The output of the latch 25 is used for controlling a pulse width modulation processing circuit (not shown). An output of the pulse width modulation circuit is used as a rotation speed control voltage for controlling the capstan motor driving circuit after being smoothed by a low-pass filter (not shown).
An output of the latch circuit 26 indicates whether or not the output of the digital frequency discriminator, i.e., the output of the latch 25 is in the linear range of the graph CNTb. If the signals F and G are both low level (referred to as the L level hereafter), the signals F and G indicate that the output of the digital frequency discriminator is lower than the lower limit of the linear detection characteristic range. If the signal F is H level and signal G is L level, the signals F and G indicate that the output of the digital frequency discriminator is in the linear detection characteristic range. If the signal F is L level and the signal G is H level, the signals F and G indicate that the output of the digital frequency discriminator is higher than the upper limit of the linear detection characteristic range.
Therefore, the signals F and G obtained by the latch circuit 26 are used to determine whether or not the output of the latch circuit 25, i.e., the frequency discrimination output of this digital frequency discriminator can be adopted for a servo control of the capstan motor (not shown). The above descriptions can be concluded, as shown in the following table.
______________________________________ F G Detection Characteristic ______________________________________ 0 0 0 (Lower than Lower limit) 1 0 Within Linear Range 0 1 1 (Higher than Upper limit) ______________________________________
The preset value NP is set so that the center of the linear range (2.sup.M /2) is obtained when the digital data FG with a center frequency fO is applied. More specifically, if the frequency of the clock signal CK is fck, the following equation is obtained. EQU fck/fO=2.sup.N -2.sup.M-1 -NP+NS,
Therefore, the preset value NP is obtained as follows, EQU NP=2.sup.N -2.sup.M-1 +NS-fck/fO
Here, NS is the number of stops of the clock signals CK in one sequence period of the sequencer 20.
FIG. 4 shows an example of the construction of a conventional digital phase comparator of a digital servo system used, for example, in VTRs. In FIG. 4, clock signal CK is applied to a sequencer 30 and an AND gate 31, through a clock input terminal 32. The sequencer 30 and the AND gate 31 constitute a system control section of this digital phase comparator, as described later. The sequencer 30 also is supplied through a data input terminal 33 with a digital data COM which is to be processed in this digital phase comparator. The digital data COM is generated by a detector (not shown) for detecting a control signal recorded on video tapes.
The sequencer 30 is so designed as to generate various control signals, such as a stop signal STOP and a latch signal LATCH, as shown in FIG. 5, in response to every pulse of the digital data COM. Those signals STOP and LATCH are generated at times, as shown in FIG. 5, in synchronization with the clock signal CK.
The construction and the operation of the conventional digital phase comparator will be explained with reference to FIGS. 4 and 5. The stop signal STOP generated by sequencer 30 is applied to the AND gate 31. Then, the stop signal STOP prohibits the clock signal CK from transmitting therethrough when the stop signal STOP is at the L level. Otherwise the clock signal CK is applied to an up-counter 34. The latch signal LATCH generated by sequencer 30 is applied to the latch input terminals of latch circuit 35 at a prescribed time after the operation of the up-counter 34 has been stabilized, for instance after five pulses of the clock signal CK have been applied. When the latch signal LATCH is applied, the latch circuit 35 latches the count data of the up-counter 34.
When the latch operation has been completed in the latch 35, the stop signal STOP becomes the H level again so that the AND gate 31 allows the clock signal CK to transmit therethrough and to be applied to the up-counter 34.
A reference signal REF is applied to a reset terminal of the up-counter 34. The reference signal REF has a rectangular waveform which is set so as to have a duty ratio, as shown in FIG. 6. When the up-counter 34 is in the L level or "0" period, the up-counter 34 is forcibly reset. In this period, a count data of the up-counter 34 is maintained at "0". When the reference signal REF becomes the H level or "1", the up-counter 34 is released from the reset condition and begins its count operation.
The up-counter 34 continues the counting of pulses of the clock signal CK until all bits of the count data become "1". The all "1" bits state of the count data is detected by an all "1" detector 36. When the all "1" detector 36 has detected the all "1" bits state, the all "1" detector 36 generates a detection output and applies the detection output to the AND gate 31 via an inverter 37. The AND gate 31 thus prohibits the clock signal CK from being applied to the up-counter 34. During the time the clock signal CK is prohibited, the up-counter 34 holds the count data of the all "1" bits state. The all "1" bits holding state continues until the up-counter 34 is forcibly reset by the reference signal REF becoming the L level.
FIG. 6 shows a series of the above operations carried out in this phase comparator, as shown in FIG. 5. By the series of operations, the count data of the up-counter 34 varies in synchronization with the reference signal REF, as shown in the drawing by a graph CNT with a trapezoidal waveform.
In the conventional phase comparator, as shown in FIG. 6, the sequencer 30 is designed to generate the latch signal LATCH, when the digital data COM arises in correspondence with the slope section of the trapezoidal waveform of the count data CNT. The latch circuit 35 then latches the count data of the up-counter 34 at the time corresponding to the prescribed portion of the scope section. As a result, the phase difference between the digital data COM and the reference signal REF is detected by the phase comparator as the latch data of the latch circuit 35. The latch data of the latch circuit 35 is applied to an external circuit (not shown), e.g., a pulse width modulation circuit. The latch data then is used for controlling a pulse width modulation processing circuit (not shown) in a manner similar to the use of the detection output of the conventional frequency discriminator, as shown in FIG. 1. An output of the pulse width modulation circuit is used as a rotation speed control voltage for controlling the capstan motor driving circuit after being smoothed by a low-pass filter (not shown).
In the above circuit, in order to obtain a zero phase difference between the reference signal REF and the digital data COM, (i.e., a zero phase comparison output of the phase comparator) at approximately the center (at 2.sup.N-1 when the number of counter bits is taken as 2) of the slope of the trapezoidal waveform, it is possible to make the reference signal REF the H level at a phase in which the reference signal REF advances the digital data COM by 2.sup.N-1.
FIG. 7 shows an example of a VTR capstan servo system comprised of the conventional digital frequency discriminator and phase comparator, as shown in FIGS. 1 and 4. For instance, a VHS system VTR is subjected to three recording speed modes of SP, LP and EP. Further the VHS system VTR is required at control a capstan motor to a various speed for a fast reproduction mode. In the N times fast reproduction mode, the digital data FG and COM have their frequencies divided by N through dividers 40 and 41 before supplying them into the frequency discriminator 42 and the phase comparator 43. The outputs of the frequency discriminator 42 and the phase comparator 43 are supplied, as an AFC (Automatic Frequency Control) voltage and an APC (Automatic Phase Control) voltage, to a gain adjustment amplifier 44 via filters 45 and 46. The gain adjustment amplifier 44 combines the frequency discrimination output and the phase comparison output together and adjusts the gain of the combined signal. The filters 45 and 46 remove ripple components of the frequency discrimination output and the phase comparison output, respectively.
The gain of the combined signal, i.e., the output of the VTR capstan servo system is reduced in the N times fast speed reproduction mode. The gain adjustment amplifier 44 is switched so that its gain is set to N times. Thereby, the loop gain of the VTR capstan servo system can provide the gain necessary to carry out a correct servo control. The output obtained by the gain adjustment amplifier 44 is supplied to a control transistor 47 of a servo motor 48 such as a capstan motor for driving a video tape 49 via a power amplifier 50.
The conventional capstan servo system for VTRs, as shown in FIG. 7, has problems when it is made in an IC (Integrated Circuit). It is possible to make into an IC the portion of the circuit of the conventional capstan servo system for VTRs shown by the diagonal shading in FIG. 7 the power amplifier 50 are coupled to the IC circuit. Therefore, the IC requires a lot of pins P1 through P5 for the connections to the external circuits of the filters 45 and 46 and the power amplifier 50. Further, the conventional capstan servo system requires the gain adjustment, as described above. Therefore, the IC configuration of the conventional capstan servo system requires an analog switch for changing the loop gain in response to the reproduction speed mode. The analog switch is also located in the external circuit of the IC.
According to the reasons, as described above, the conventional capstan servo system also has a problem that the IC circuit becomes large in chip size.